1. Field of the Invention
The present invention relates to a multiple-gate MOS transistor using a silicon substrate and a method of manufacturing the same, and more particularly, to a multiple-gate metal oxide semiconductor field effect transistor (MOSFET) in which a channel region having a nano-sized linewidth is connected to a substrate, and a streamline-shaped (∩) channel and a source and a drain having reduced series resistance are provided, and a method of manufacturing the same.
2. Discussion of Related Art
As semiconductor device manufacturing technology develops, devices are being scaled down in size and endeavors for increasing their operation speed to improve performance are being made. Accordingly, today, even a metal oxide semiconductor field effect transistor (MOSFET), a fundamental electronic device, is being continuously scaled down in size. However, in a general MOSFET, if a channel length is reduced to 100 nm or less, device on/off control ability based on a gate voltage is reduced due to a so-called short channel effect.
In order to overcome this drawback, a double-gate structure in which gate electrodes are formed at both sides of a channel region through which current flows has been proposed. In the double-gate structure, since the gate electrodes are formed at both sides of the channel region, current control ability in the channel region based on a gate voltage is greatly improved, thereby suppressing the short channel effect and providing the advantage of further miniaturized device. Further, a “wrap-around” gate structure or a “surround” gate structure, which is an extension of the concept of the double-gate structure, has been proposed. In this gate structure as well, a control ability based on a gate voltage is improved.
In a field effect transistor of an ideal double-gate structure, front and rear gates, and even source and drain, are self-aligned. Therefore, parasitic resistance is reduced. In recent years, a FinFET having a double-gate structure with a self-aligned gate has been developed using an unaltered conventional semiconductor process. This has the advantage of high compatibility with conventional planar structure semiconductor technology.
FIG. 1 is a perspective view illustrating a conventional double-gate FinFET.
A silicon on insulator (SOI) substrate having a stacked structure including a silicon layer 10, a buried oxidation layer 11, and a single crystalline silicon layer 12 is used. A single crystalline silicon pattern having a Fin structure is obtained by patterning the single crystalline silicon layer 12, and defines source and drain regions 12a, a channel region 12b, and an extension region 12c. The channel region 12b and the extension region 12c between the source and drain regions 12a are formed to be narrower than the source and drain regions 12a. 
A mask pattern 13 for preventing concentration of electric field and channel formation is formed on the single crystalline silicon pattern having the channel region 12b, a gate oxide layer 14 is formed on a surface of the single crystalline silicon pattern, and a gate electrode 15 is formed on an oxide layer 11 and the gate oxide layer 14 disposed on the channel region 12b. 
However, there are drawbacks in that, since the double-gate FinFET is manufactured on the SOI substrate, manufacturing cost is much higher than when manufactured on a bulk silicon substrate, and an off-current is increased, thereby causing poor thermal conduction. And, since a device is not connected with the substrate, a floating-body effect is caused, thereby deteriorating performance of the device.
In order to overcome these drawbacks, a double-gate FinFET device using a bulk silicon substrate has been proposed.
FIG. 2 is a perspective view illustrating a conventional double-gate FinFET using a bulk silicon substrate.
The proposed double-gate FinFET uses a bulk silicon substrate 20, and includes an active region having a Fin structure connected to a top and center of the bulk silicon substrate 20 and formed of single crystalline silicon; a first oxide layer 24 formed up from the surface of the bulk silicon substrate to a predetermined height with respect to the Fin active region 26; a nitride layer 27 thickly formed outside of the first oxide layer 24; a gate oxide layer 21 surrounding the Fin active region; a second oxide layer 28 formed outside of the nitride layer 27; a gate 25 formed on the first and second oxides 24 and 28; and source/drain regions 22a formed at both sides of the Fin active region 26 except where the Fin active region 26 overlaps the gate 25.
Since the FinFET uses a bulk wafer, it is inexpensive to manufacture, and since the Fin active region 26 having a silicon structure is connected with the substrate 20, not only can the drawback of the floating-body effect be solved, but device characteristics can be improved as well owing to good thermal conduction.
However, in the double-gate FinFET using the bulk silicon substrate, there are technological limitations to overcome. The same limitations also apply to the double-gate device using the SOI substrate of FIG. 1. Therefore, it is very important to overcome these limitations as stated below.
First, in order to manufacture a FinFET having stable operation characteristics, the width of the channel region should be no more than about half the length of the gate. In order to form such a channel width, nano patterning technology is required. Accordingly, delicate photolithography technology or technology such as ashing and trimming is required. When general electron-beam photolithography technology is used, the channel region undergoes a relatively large change in width, thereby increasing relative deviation of device characteristics and also lowering throughput. When the channel width is determined using ashing and trimming technology, uniformity is greatly diminished.
Second, when the Fin structure having the single crystalline silicon pattern is formed, it is not only difficult to form the silicon pattern, but also, since the channel region of the Fin structure is formed to have a rectangular shape, a corner effect of top corners storing charges due to a local concentration of electric field, thereby deteriorating device reliability.
Third, since the source and drain extension region is formed to have the same thickness and width as the channel region, parasitic resistance is high and thus a current driving ability of the device is remarkably reduced. In order to solve this problem, an elevated source/drain structure in which single crystalline silicon or silicon germanium (SiGe) is epitaxially grown at the source and drain regions has been introduced. But such a structure has the drawback of requiring complex processing.